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Espressif Systems /ESP32-C3 /SPI2 /DMA_INT_RAW

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Interpret as DMA_INT_RAW

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA_INFIFO_FULL_ERR_INT_RAW)DMA_INFIFO_FULL_ERR_INT_RAW 0 (DMA_OUTFIFO_EMPTY_ERR_INT_RAW)DMA_OUTFIFO_EMPTY_ERR_INT_RAW 0 (SLV_EX_QPI_INT_RAW)SLV_EX_QPI_INT_RAW 0 (SLV_EN_QPI_INT_RAW)SLV_EN_QPI_INT_RAW 0 (SLV_CMD7_INT_RAW)SLV_CMD7_INT_RAW 0 (SLV_CMD8_INT_RAW)SLV_CMD8_INT_RAW 0 (SLV_CMD9_INT_RAW)SLV_CMD9_INT_RAW 0 (SLV_CMDA_INT_RAW)SLV_CMDA_INT_RAW 0 (SLV_RD_DMA_DONE_INT_RAW)SLV_RD_DMA_DONE_INT_RAW 0 (SLV_WR_DMA_DONE_INT_RAW)SLV_WR_DMA_DONE_INT_RAW 0 (SLV_RD_BUF_DONE_INT_RAW)SLV_RD_BUF_DONE_INT_RAW 0 (SLV_WR_BUF_DONE_INT_RAW)SLV_WR_BUF_DONE_INT_RAW 0 (TRANS_DONE_INT_RAW)TRANS_DONE_INT_RAW 0 (DMA_SEG_TRANS_DONE_INT_RAW)DMA_SEG_TRANS_DONE_INT_RAW 0 (SEG_MAGIC_ERR_INT_RAW)SEG_MAGIC_ERR_INT_RAW 0 (SLV_BUF_ADDR_ERR_INT_RAW)SLV_BUF_ADDR_ERR_INT_RAW 0 (SLV_CMD_ERR_INT_RAW)SLV_CMD_ERR_INT_RAW 0 (MST_RX_AFIFO_WFULL_ERR_INT_RAW)MST_RX_AFIFO_WFULL_ERR_INT_RAW 0 (MST_TX_AFIFO_REMPTY_ERR_INT_RAW)MST_TX_AFIFO_REMPTY_ERR_INT_RAW 0 (APP2_INT_RAW)APP2_INT_RAW 0 (APP1_INT_RAW)APP1_INT_RAW

Description

SPI DMA interrupt raw register

Fields

DMA_INFIFO_FULL_ERR_INT_RAW

1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others.
DMA_OUTFIFO_EMPTY_ERR_INT_RAW

1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others.
SLV_EX_QPI_INT_RAW

The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.
SLV_EN_QPI_INT_RAW

The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.
SLV_CMD7_INT_RAW

The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.
SLV_CMD8_INT_RAW

The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.
SLV_CMD9_INT_RAW

The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.
SLV_CMDA_INT_RAW

The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.
SLV_RD_DMA_DONE_INT_RAW

The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.
SLV_WR_DMA_DONE_INT_RAW

The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.
SLV_RD_BUF_DONE_INT_RAW

The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.
SLV_WR_BUF_DONE_INT_RAW

The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.
TRANS_DONE_INT_RAW

The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.
DMA_SEG_TRANS_DONE_INT_RAW

The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred.
SEG_MAGIC_ERR_INT_RAW

The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.
SLV_BUF_ADDR_ERR_INT_RAW

The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.
SLV_CMD_ERR_INT_RAW

The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.
MST_RX_AFIFO_WFULL_ERR_INT_RAW

The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.
MST_TX_AFIFO_REMPTY_ERR_INT_RAW

The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
APP2_INT_RAW

The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.
APP1_INT_RAW

The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data